Signal Edge Solutions
Technical Library
Articles
Mitigating Ground Loop Errors in High-Current PDN Measurements: Validating Measurement Accuracy Across Oscilloscope Platforms
April 2026
Link to Article
Abstract:
The rapid growth in data centers, AI, and supercomputing demands significantly faster edge rates at the package and PCB levels, necessitating superior power delivery network (PDN) measurement solutions. As currents increase and voltage rails shrink, managing fluctuations becomes a critical challenge. Issues such as jitter, frequency-dependent loss, and crosstalk can lead to significant voltage sags and ground bounce. These disturbances directly impact signal integrity through power supply-induced jitter and amplitude noise. Consequently, high-fidelity PDN analysis is now an essential phase of the digital design process.
Simulating DC-DC Converter Efficiency More Accurately With State-Space Averaging VRM Models
January 2026
​Link to Article
Causality in Practice: How Frequency Sampling and Bandwidth Shape Time-Domain Fidelity
September 2025
​Link to Article
How to Simulate Low Voltage, High Power 2000 Amps to a Dynamic Digital Load
March 2025
Link to Article
Abstract:
Hardware engineers are learning the hard way that power integrity (PI) requires electromagnetic (EM) simulation of the printed circuit board (PCB) power delivery network (PDN). Traditional rules-of-thumb and leveraging data sheet examples are not an option as designs move from hundreds of Amps (A) to thousands. 1000 A across a 100 microhm (µΩ) PCB PDN is still 100 millivolts (mV) of IR drop and 100 Watts (W) of power dissipating as heat. This is one of the fundamental reasons for transporting power at a higher voltage and lower current for as far as possible. Less power lost in the path to the load. The other reason is impedance. Power rail voltage ripple is a direct result of dynamic di/dt currents interacting with the path impedance. When currents go up, the target impedance must go down to keep power rail voltage ripple within specified limits. Controlling the power delivery DC resistance and the parasitic path inductances of the PCB is a critical part of creating a Digital Twin model for designing a 2000 A PDN for a dynamic digital load.
Who Put that Inductor in My Capacitor
May 2024
Link to Article
Abstract:
Accurate measurement and characterization of capacitors are essential for designing optimal power distribution networks (PDNs) in a modern printed circuit board assembly (PCBA) and application specific integrated circuits (ASICs). Vendor provided capacitor models often include additional inductance from the capacitor mount used for measurement, impacting the PDN simulation and performance. This paper highlights the importance of having accurate capacitor models by demonstrating their impact on PDNs. The inclusion of additional inductance in vendor provided capacitor models leads to inaccurate representation of the capacitor’s impedance over frequency. De-embedding the PCB mount from a measurement-based model removes the added inductance, removing model error and enabling higher fidelity PDN simulation.  Accurate capacitor modeling ensures the design meets the power integrity requirements needed for design signoff by removing simulation errors that can occur in the PDN. This paper uses a system-level PDN, comprised of a state-space average voltage regulator module (VRM) model, PCB, package, and die to provide a comparative simulation analysis in frequency domain as well as time domain between vendor models and measurement-based capacitor models. Where the overall objective is to demonstrate how important it is to have accurate capacitor models as part of a PDN design for sign-off.
Abstract:
EDICON 2023 - What is Enough? VDDQ Package Power Integrity Analysis with a DDR4 PHY
January 2024
Link to Article
As voltage margins for power rails continue to decrease, end-to-end power integrity modeling is already difficult without having to be concerned if all the models that are part of your simulation are correct. As system designers, we typically expect and, in most cases, assume that all the models from vendors are correct. So, what does an engineer do if one of the models needed for a power integrity simulation is not correct? What if this is a die model? How does an engineer verify if the die model is accurate or has enough on-die capacitance to manage high-frequency currents? ​ This presentation will demonstrate how to build and model an end-to-end power Integrity model for a DDR4 PHY and package. As part of this discussion, analysis will be shown to determine if the DDR PHY integrated into a custom ASIC has sufficient on-die capacitance for the respective DDR4 power domain. At the end of this presentation, engineers will understand how to model and develop an end-to-end power Integrity model for their ASIC while determining if their ASIC has sufficient on-die capacitance for their application.
The Challenge of Measuring a 40 uOhm (2000 Amp) PDN with a 2-Port Probe
Abstract:
In this three-part Extreme Measurements article, Steve Sandler and I discuss the CMRR requirements to make sub-40 uOhm impedance measurements on a PDN with a 2-port probe.
APEC 2023 Professional Seminar - How Power Integrity Is Changing the World of Power Electronics
Abstract:
As voltage margins for power rails continue to decrease, end-to-end power integrity modeling is already difficult without having to be concerned if all the models that are part of your simulation are correct. As system designers, we typically expect and, in most cases, assume that all the models from vendors are correct. So, what does an engineer do if one of the models needed for a power integrity simulation is not correct? What if this is a die model? How does an engineer verify if the die model is accurate or has enough on-die capacitance to manage high-frequency currents? ​ This presentation will demonstrate how to build and model an end-to-end power Integrity model for a DDR4 PHY and package. As part of this discussion, analysis will be shown to determine if the DDR PHY integrated into a custom ASIC has sufficient on-die capacitance for the respective DDR4 power domain. At the end of this presentation, engineers will understand how to model and develop an end-to-end power Integrity model for their ASIC while determining if their ASIC has sufficient on-die capacitance for their application.
Abstract:
Ultra-Ultra-Low Impedance (4 Micro-Ohm) Measurements
July 2022
Link to Article
In this Extreme Measurements article, I discuss the lowered impedance targets that are a result of the increasing amount of current necessary for modern processor solutions. Read on to learn how to achieve impedance targets below 10 uOhms.
Abstract:
Measuring the Bulk Dielectric Constant (Dk) on a Microstrip With
a TDR
September 2021
Link to Article
Most modern circuit designs depend on accurate logic signals at the logic receiver. This assurance is based on the careful design of the signal path impedance, including printed circuit board (PCB) transmission lines, interconnects, vias, and cables. If you have designed a controlled impedance transmission line based on a PCB stack-up, how do you know if the PCB fabrication house or another vendor built your stack-up to meet your controlled impedance specification? In fact, we have found, even after discussion with various laminate manufacturers, that the majority of dielectric constants specified in the vendor datasheet have uncertainty, with a lot of variability. This creates a call to action to measure these materials to get it right.
Abstract:
Common Cents Impedance Measurements
September 2021
Link to Article
A technical article exploring different calibration techniques, with a 2-port probe, to archive to sub-100μΩ impedance measurements with U.S. pennies.
Abstract:
Calibrating the 2-Port Probe for Low Impedance PDN Measurements
May 2021
Link to Article
Benjamin Dannan and Steve Sandler teamed up to explore the tradeoffs for various calibration methods and offer some recommendations and considerations to make accurate sub-milliohm impedance measurements.
DesignCon 2020 - Signal Integrity Characterization of Via Stubs on High Speed DDR4 Channels
June 2020
Link to Article
Abstract:
As DDR data transmission rates continue to increase, the signal integrity of the DDR channel has become one of the most critical concerns. This article takes an extensive look at the impact of via stubs on the impedance of the signal lines on DDR4 memory, including test cases and ways to optimize design.
Abstract:
How Ground Bounce Can Ruin Your Day
February 2020
Link to Article
Low-speed printed circuit board (PCB) designs now have to deal with high-speed switching problems. This article examines the ground bounce generated from an LCD assembly while evaluating the impact of the ground bounce on the system level EMI. Three solution strategies to mitigate the ground bounce are analyzed, the pros and cons of each strategy are provided along with the test results.
Abstract:
Addressing EMC Challenges with In-house EMC Pre-compliance Testing
March 2020
Link to Article
This article discusses how to build an in-house EMC pre-compliance testing setup to improve the success rate in EMC compliance testing.
Presentations
Precision Power Measurements for Voltage Regulator Characterization and POL Modeling
March 2025
​Link to Slide Deck
Keysight EDA Connect Tour 2025 - Crosstalk Analysis and Mitigation for 16 Gb/s UCIe Chiplet Interfaces using Keysight Chiplet PHY Designer
March 2025
Link to Slide Deck
Abstract:
Multi-die packaging with chiplets is crucial for high-performance data centers and aerospace and defense solutions, demanding advanced packaging technologies. The UCIe Consortium's 2.0 specification promises significant bandwidth, density, and power efficiency advancements. This work focuses on the signal integrity challenges posed by high-speed UCIe interconnects. Modern chiplet designs feature hundreds of single-ended signals operating at 16 Gb/s, with 32 Gb/s on the horizon. Accurate modeling of these dense interconnects is critical for reliable package substrate design. This presentation demonstrates a workflow for analyzing and mitigating crosstalk in a 16 Gb/s UCIe die-to-die interface using Keysight ADS Chiplet PHY Designer. We employ a single macro to represent the interface and analyze crosstalk effects from multiple single-ended nets within the same macro. By identifying the worst-case aggressor, we strategically incorporate additional return vias to enhance signal integrity and improve eye diagram quality. This workflow provides a robust approach for the sign-off of advanced package designs for demanding chiplet applications.
Abstract:
Analyzing Large Signal Phenomena and Crosstalk in Time & Frequency Domain and Avoiding Ground Loop Effects
2025
Link to Slide Deck
As electronic designs evolve, managing power fluctuations becomes increasingly challenging due to lower voltage levels and tighter component tolerances. With rising data rates, shrinking supply voltages, and higher integration densities, issues such as jitter, noise, frequency-dependent loss, reflections, and crosstalk are more common than ever. These factors can significantly affect power rails, resulting in voltage sag and ground bounce. Power rail disturbances, in return, have an increasing effect on signal integrity, particularly through power supply-induced jitter and amplitude noise. Thus, analyzing power integrity and the performance of the power delivery network (PDN) on a printed circuit board (PCB) is now an essential part of the digital design process. In this session, you will learn more about: •Analyzing large and small signal phenomena and the corresponding way of testing them •Measuring PDN Crosstalk in the time and frequency domain •Ground loop effects and how to avoid them
Abstract:
Correcting Ground Loop Errors in Multi-Channel Oscilloscope Measurements with Power Rail and other Single-Ended Probes
August 2024
Link to Slide Deck
Power rail probes are hugely popular for measuring voltage noise. As core current increases and voltage falls, the margins get smaller. Placing more than one probe in different locations on the printed circuit board (PCB) will add ground loop noise to your measurements. This is true for power rail probes and all single-ended voltage probes. Multi-channel oscilloscopes have become ubiquitous solutions to support voltage noise measurements in multiple power domain applications. When acquiring signals and making low-noise measurements, engineers often focus on the oscilloscope’s key features, such as bandwidth and dynamic range. However, as voltage compliance requirements become more stringent, understanding the noise impact of our ground loop from our probing solutions is critical, especially when assessing voltage ripple in power systems. ​ Unfortunately, ground loops are common in real-world measurement setups and pose a significant challenge when performing multi-channel measurements on the same Device Under Test (DUT). These ground loops introduce additional noise errors into measurement results, rendering even high-bandwidth oscilloscopes and expensive probing solutions ineffective. This presentation will show how to mitigate the impacts of ground loops by adding a coaxial isolator to significantly improve measurement accuracy. The isolator improves the CMRR performance of the probes, greatly improving the accuracy of multi-channel oscilloscope measurements using power rail probes and other single-ended probing solutions. ​ Addressing ground loop errors is paramount for achieving reliable, accurate multi-channel measurements. Engineers must be aware of these challenges and take appropriate steps to mitigate their impact on measurement accuracy.
Abstract:
DesignCon 2024 - Design, Simulation and Validation of a 2000-Amp Core Power Rail
January 2024
Link to Slide Deck
This paper will demonstrate how to measure, model, and validate a scalable, 2k-Amp core power rail. The technological growth in Data Centers, AI, Graphics, and Super-Computing has pushed the core power rail current to 2k-Amps and is climbing. Designing such a power rail is a complex task, involving architectural design choices as well as simulation and validation challenges. Lower core voltages reduce power but also reduce operating noise margins. Combined, these require greater expertise in design choices, much greater simulation accuracy, and more rigorous validation of the power rail. This paper will address this 2k-Amp project from the beginning with a variety of architectural design choices and resulting modeling and simulation challenges, including cascaded VRMs, current sharing, and thermal simulation. The assessment of PDN impedance has become a well-published mantra, and yet core power rail validation generally requires time domain testing as well as impedance testing, which presents yet greater challenges. Therefore, the final validation of this design is done using time domain testing at full ASIC power with dynamic modulation at package speeds of up to 100MHz to address the large signal response phenomenon. Simulation to measurement correlation will be shown for electrical and thermal behavior.
Abstract:
DesignCon 2024 - Unmasking Voltage Regulator Instability: What Vendor Reference Designs Aren't Telling You
January 2024
Link to Slide Deck
Voltage regulator vendor reference designs serve as indispensable instruments for designers aiming to integrate a vendor’s voltage regulator into their specific design projects. While these evaluation boards offer valuable insights into regulator performance, it is essential for designers to recognize that these boards are engineered to cater to a diverse range of applications, rather than being tailored to a specific systems' requirements. This demonstration will shed light on the inherent instability often observed in these vendor reference designs through the utilization of the non-invasive stability measurement (NISM) technique.
Abstract:
EDICON 2023 - What is Enough? VDDQ Package Power Integrity Analysis with a DDR4 PHY
October 2023
Link to Slide Deck
As voltage margins for power rails continue to decrease, end-to-end power integrity modeling is already difficult without having to be concerned if all the models that are part of your simulation are correct. As system designers, we typically expect and, in most cases, assume that all the models from vendors are correct. So, what does an engineer do if one of the models needed for a power integrity simulation is not correct? What if this is a die model? How does an engineer verify if the die model is accurate or has enough on-die capacitance to manage high-frequency currents? ​ This presentation will demonstrate how to build and model an end-to-end power Integrity model for a DDR4 PHY and package. As part of this discussion, analysis will be shown to determine if the DDR PHY integrated into a custom ASIC has sufficient on-die capacitance for the respective DDR4 power domain. At the end of this presentation, engineers will understand how to model and develop an end-to-end power Integrity model for their ASIC while determining if their ASIC has sufficient on-die capacitance for their application.
APEC 2023 Professional Seminar - How Power Integrity Is Changing the World of Power Electronics
Abstract:
As voltage margins for power rails continue to decrease, end-to-end power integrity modeling is already difficult without having to be concerned if all the models that are part of your simulation are correct. As system designers, we typically expect and, in most cases, assume that all the models from vendors are correct. So, what does an engineer do if one of the models needed for a power integrity simulation is not correct? What if this is a die model? How does an engineer verify if the die model is accurate or has enough on-die capacitance to manage high-frequency currents? ​ This presentation will demonstrate how to build and model an end-to-end power Integrity model for a DDR4 PHY and package. As part of this discussion, analysis will be shown to determine if the DDR PHY integrated into a custom ASIC has sufficient on-die capacitance for the respective DDR4 power domain. At the end of this presentation, engineers will understand how to model and develop an end-to-end power Integrity model for their ASIC while determining if their ASIC has sufficient on-die capacitance for their application.
Abstract:
DesignCon 2023 - VRM Modeling and Stability Analysis for the Power Integrity Engineer
January 2023
Link to Slide Deck
In the world of power electronics, the focus is on the power supply, and the load is modeled as a simple resistor. In the world of power integrity, the focus is on the decoupling capacitors required for the digital load, and the power supply is modeled as a simple resistor in series with an inductor. In the real world, neither assumption solves the problem of simulating the power delivery ecosystem with switching power supply control loops, gigabit switching digital loads, and a PCB network of filtering and decoupling components. The challenge is how to simulate the Power Integrity ecosystem and include the feedback loop and switching noise of a switch mode power supply (SMPS) without waiting days for the simulation results. The solution presented here uses control loop theory state space equations to create a behavioral model of an SMPS that allows for fast simulation. This Sandler State Space Average Model previously published [1] has the fidelity to include the dynamic control loop behavior for stability assessment, large signal and small signal noise ripple, and power supply rejection ratio. The model also works with the Non-Invasive Stability Measurement method to assess the control loop phase margin from simple output impedance data.
Abstract:
DesignCon 2023 - Chiphead - Hands-On PDN Impedance and Calibration Basics
January 2023
Link to Slide Deck
You have probably heard of calibration, de-embedding, and fixture removal for network analyzer measurements, but do you know how to do it for a 2-port shunt low-impedance measurement? Impedance measurements are a must-have skill for Power Integrity engineers. The measurements provide models for Capacitors, Resistors, and Inductors that work in both time and frequency domain simulations. Impedance measurements are also critical for verifying the performance stability of a power delivery network (PDN). In this session, you’ll learn the difference between these terms. You’ll learn, with demonstrations, how to remove the impact of fixturing using calibration and de-embedding steps. The process works for both connectorized devices or with PCB browser probes to provide accurate measurements that are compatible with your PCB EM simulator.
Abstract:
EDICON 2022 - Stability and Performance Improvement with Feedback in VRM Transconductance Error Amplifiers - a Case Study Using the Sandler State Space Average Model
October 2022
Link to Slide Deck
The voltage regulator module (VRM) is the foundation of power integrity. Due to their wide bandwidth and low cost, most newer VRM controllers employ transconductance feedback amplifiers, with the VRM manufacturers recommending a shunt compensation for the error amplifier design. However, most VRM designers and power integrity engineers may not be aware that they have another choice to improve the sensitivity and performance of their VRM design. The better performance of a current mode VRM with series compensation for the error amplifier is clearly demonstrated with simulations using the Sandler state-space average VRM model. Additional analysis and discussion will be provided to show how the VRM’s performance has improved stability, reduced gain sensitivity, and overall improved performance with a series compensation network. A VRM case study will be presented in this technical session to show these performance improvements using the Sandler State Space Average model in Keysight PathWave ADS.
Abstract:
DesignCon 2022 - Improved Methodology to Accurately Perform System Level Power Integrity Analysis Including an ASIC Die
April 2022
Link to Slide Deck
The ASIC-based systems of today and tomorrow can no longer be designed by rules of thumb when it comes to power integrity. The current methods of evaluating power integrity for an ASIC die on a substrate are generally lacking sufficient accuracy. The key element for system-level PDN analysis is a chip die model, which requires specialized EDA tools to create. These EDA solutions typically create chip models using either vector-based or vector-less dynamic current profiles. Vector-based chip model solutions are challenging to create and typically do not cover the complete ASIC die use case. In addition, the benefits of models created for the die, substrate, and PCB have multiple possible configurations such as lumped, distributed, looped and partial. This paper provides a novel workflow on the benefits of using lumped-looped models to improve efficiency, while achieving accuracy, and reducing the overall risk to a given system PDN. Lastly, this paper provides an improved methodology on how to know if the voltage ripple at the die bumps on a substrate is violating the defined specification of the ASIC and shows the methods on how to evaluate the PDN target impedance across a system.
DesignCon 2022 - DDR4-3200 FPGA-Based System With Interposer Power-Aware SI Simulation to Measurement Correlation
April 2022
Link to Slide Deck
Abstract:
DDR4-3200 SSO channel modeling is further challenged to ensure DQ compliance specification for eye-opening at an ultra-low 1E-16 BER. As DDR4-3200 edge rates approach
Abstract:
EDICON 2021 - Partial Inductance - the Secret to Correlating Simulation to Measurement
October 2021
Link to Slide Deck
There's confusion about the measurement of capacitors, and particularly the series inductance or ESL. Different manufacturers calibrate or de-embed their measurement differently, making it difficult to compare one vendor to another. The differences between these measurements represent different locations of the measurement reference plane. When correlating EM simulation and measurement results, where should the reference plane be for the capacitor measurement? Why does the target impedance measurement show much higher inductance than the simulator? Why do some experts recommend measuring impedance from both sides of the PCB and not just one side? In this session, Steve Sandler, Heidi Barnes, and I will provide analysis that answers all of these questions and more!
Abstract:
PROJECT X DDR4-2400 Signal Integrity Analysis
April 2021
Link to Slide Deck
Northrop Grumman Case Study: Rigorous Design Analysis of a DDR4 DIMM-Based System Analysis shows multi-board simulation model with custom ASIC, MCM package, PCBA, UDIMM, and RDIMM models.
Abstract:
EDICON 2020 DDR4-3200 Channel Modeling and Signal Integrity Analysis Using an FGPA
October 2020
Link to Slide Deck
A presentation with the Xilinx VCK190 using the Versal on how to develop a DDR4-3200 simulation model. This looks at signal integrity in the channel, such as insertion loss, crosstalk, and tuning the DDR4 eye using ODT.
Podcasts
Abstract:
DesignCon 2026: Kick-Off Episode with the Dream Team of Power Integrity
February 2026
Link to Podcast Episode
In this episode Judy Warner talks with Steve Sandler, Heidi Barnes and Ben Dannan, who are three leading experts in Power Integrity and combined are presenting 17 talks at DesignCon 2026, Including a tutorial they will present together. They have all also been nominated for Engineer of the Year at DesignCon this year. Enjoy learning about the breakthrough they are creating together to create solutions for AI, Data Centers and HPC applications that will empower engineers both today and for the future.
Abstract:
Abstract:
Product Design Process | Navigating the Electronics Engineer's Journey with Ben Dannan & Heesoo Lee
January 2024
Link to Podcast Episode
From concept to creation, this video is your guide to mastering the product design process. Don't miss out on the wisdom shared by these experts! Join us on a journey through the intricacies of product design with electronics engineers Ben Dannan and Heesoo Lee. Discover the roadmap, uncover key insights, and gain practical tips as they navigate the challenging terrain of the electronics engineer's journey.
Abstract:
DDR VDDQ | VDDQ Package Power Integrity for DDR4/5 | Expert - Ben Dannan
October 2023
Link to Podcast Episode
Ben Dannan of Signal Edge Solutions and Principal Engineer at a Tier One Defense Contractor discusses a presentation he'll be giving at EDI Con Online next week. His talk is entitled: What is Enough VDDQ Package PI Analysis for DDR4/5. His talk will cover an actual use case he and his colleague encountered and will share techniques on how to "sanity check" vendor IP models to ensure accurate simulation that will result in positive implications across the whole system.
Abstract:
Discussion: EDICON 2023 - What is Enough? VDDQ Package Power Integrity Analysis with a DDR4 PHY
September 2023
Link to Podcast Episode
As voltage margins for power rails continue to decrease, end-to-end power integrity modeling is already difficult without having to be concerned if all the models that are part of your simulation are correct. As system designers, we typically expect and, in most cases, assume that all the models from vendors are correct. So, what does an engineer do if one of the models needed for a power integrity simulation is not correct? What if this is a die model? How does an engineer verify if the die model is accurate or has enough on-die capacitance to manage high-frequency currents? ​ This presentation will demonstrate how to build and model an end-to-end power Integrity model for a DDR4 PHY and package. As part of this discussion, analysis will be shown to determine if the DDR PHY integrated into a custom ASIC has sufficient on-die capacitance for the respective DDR4 power domain. At the end of this presentation, engineers will understand how to model and develop an end-to-end power Integrity model for their ASIC while determining if their ASIC has sufficient on-die capacitance for their application.
Abstract:
Systems Engineering with an Aviator's "Mission" Mindset
March 2023
Link to Podcast Episode
Prime Military Contractor Technical Fellow and Air Force Pilot Ben Dannan discusses his unique perspective on engineering. Both his time in the air and his time on the bench have worked together to make him a more effective systems engineer. (This is part 1 of a 3-part series)
Abstract:
VRM Modeling & Stability for Power Integrity Engineers
January 2023
Link to Podcast Episode
n this episode Judy Warner talks with Steve Sandler, Heidi Barnes and Ben Dannan, who are three leading experts in Power Integrity and combined are presenting 17 talks at DesignCon 2026, Including a tutorial they will present together. They have all also been nominated for Engineer of the Year at DesignCon this year. Enjoy learning about the breakthrough they are creating together to create solutions for AI, Data Centers and HPC applications that will empower engineers both today and for the future.
Abstract:
DDR4, Signal Integrity, and Power Integrity in PCB Design with Benjamin Dannan
July 2022
Link to Episode
As voltage margins for power rails continue to decrease, end-to-end power integrity modeling is already difficult without having to be concerned if all the models that are part of your simulation are correct. As system designers, we typically expect and, in most cases, assume that all the models from vendors are correct. So, what does an engineer do if one of the models needed for a power integrity simulation is not correct? What if this is a die model? How does an engineer verify if the die model is accurate or has enough on-die capacitance to manage high-frequency currents? ​ This presentation will demonstrate how to build and model an end-to-end power Integrity model for a DDR4 PHY and package. As part of this discussion, analysis will be shown to determine if the DDR PHY integrated into a custom ASIC has sufficient on-die capacitance for the respective DDR4 power domain. At the end of this presentation, engineers will understand how to model and develop an end-to-end power Integrity model for their ASIC while determining if their ASIC has sufficient on-die capacitance for their application.
Technical Papers
Abstract:
Modeling and Measuring Large Signal PDN Crosstalk and Ground Bounce with a Multi-Phase VRM System Using a Fast Multi-Domain BGA Step Load
February 2026
Link to Paper
Modern AI and datacenter systems, equipped with complex multi-domain Power Distribution Networks (PDNs), grapple with substantial challenges stemming from large-signal crosstalk and ground bounce. These issues are particularly prevalent under fast, dynamic, multi-domain step loads. Such transient conditions, caused by significant current fluctuations on one PDN, can induce considerable voltage noise on neighboring power rails due to mutual electromagnetic coupling. Concurrently, rapid high-current switching within multi-phase Voltage Regulator Modules (VRMs) can generate substantial ground bounce in parasitic return paths. Both of these phenomena degrade power integrity, adversely affecting sensitive on-die circuits and the VRM's transient response. This work presents a rigorous investigation into modeling and measuring these challenging large-signal phenomena. This paper details a comprehensive approach to model and measure these critical large-signal effects, leveraging full-wave electromagnetic (EM) simulations for accurate parasitic extraction. These extractions are then integrated into transient circuit co-simulations with behavioral VRM models capable of handling large current swings. Our methodology further incorporates precise probing techniques and experimental validation to isolate and quantify induced noise and ground bounce. The ultimate goal is to optimize PDN stability, mitigate unwanted noise, and enhance overall system performance in high-performance digital environments.
Abstract:
DesignCon 2025 - Methods to Model and Measure Noise Mitigation with Embedded Capacitors in High Current PDNs for AI and Cloud Compute
February 2026
Link to Paper
The rapid growth in Data Centers, AI, and supercomputing demands significantly faster edge rates at the package and PCB levels, necessitating superior power delivery network (PDN) solutions. While traditional VRMs and bulk capacitors dominate at lower frequencies, the impact and effectiveness of embedded capacitors in high-current PDNs remain critical for achieving high performance. This paper explores various embedded capacitor technologies and their layout considerations within PCB and package stackups. Through detailed simulation and measurement, we analyze the influence of embedded capacitors on system performance, noise reduction, and power delivery efficiency in AI/datacenter applications. We specifically investigate how embedded capacitors impact large signal phenomena, validating findings through both measurements and simulation, and present methods for effectively modeling small signal analysis with these components. We also discuss manufacturing challenges and examine the impact of lateral versus vertical power delivery systems; specifically, we address how vertical power, while more efficient and higher performance due to proximity to the chip, removes the ability to place backside decoupling. This work provides comprehensive insights into leveraging embedded capacitors to optimize PDN design for next-generation ASICs.
Abstract:
DesignCon 2024 - Design, Simulation and Validation of a 2000-Amp Core Power Rail
January 2024
Link to Paper
This paper will demonstrate how to measure, model, and validate a scalable, 2k-Amp core power rail. The technological growth in Data Centers, AI, Graphics, and Super-Computing has pushed the core power rail current to 2k-Amps and is climbing. Designing such a power rail is a complex task, involving architectural design choices as well as simulation and validation challenges. Lower core voltages reduce power but also reduce operating noise margins. Combined, these require greater expertise in design choices, much greater simulation accuracy, and more rigorous validation of the power rail. This paper will address this 2k-Amp project from the beginning with a variety of architectural design choices and resulting modeling and simulation challenges, including cascaded VRMs, current sharing, and thermal simulation. The assessment of PDN impedance has become a well-published mantra, and yet core power rail validation generally requires time domain testing as well as impedance testing, which presents yet greater challenges. Therefore, the final validation of this design is done using time domain testing at full ASIC power with dynamic modulation at package speeds of up to 100MHz to address the large signal response phenomenon. Simulation to measurement correlation will be shown for electrical and thermal behavior.
Abstract:
DesignCon 2023 - VRM Modeling and Stability Analysis for the Power Integrity Engineer
January 2023
Link to Paper
In the world of power electronics, the focus is on the power supply, and the load is modeled as a simple resistor. In the world of power integrity, the focus is on the decoupling capacitors required for the digital load, and the power supply is modeled as a simple resistor in series with an inductor. In the real world, neither assumption solves the problem of simulating the power delivery ecosystem with switching power supply control loops, gigabit switching digital loads, and a PCB network of filtering and decoupling components. The challenge is how to simulate the Power Integrity ecosystem and include the feedback loop and switching noise of a switch mode power supply (SMPS) without waiting days for the simulation results. The solution presented here uses control loop theory state space equations to create a behavioral model of an SMPS that allows for fast simulation. This Sandler State Space Average Model previously published [1] has the fidelity to include the dynamic control loop behavior for stability assessment, large signal and small signal noise ripple, and power supply rejection ratio. The model also works with the Non-Invasive Stability Measurement method to assess the control loop phase margin from simple output impedance data.
Abstract:
DesignCon 2022 - Improved Methodology to Accurately Perform System Level Power Integrity Analysis Including an ASIC Die
April 2022
Link to Paper
The ASIC-based systems of today and tomorrow can no longer be designed by rules of thumb when it comes to power integrity. The current methods of evaluating power integrity for an ASIC die on a substrate are generally lacking sufficient accuracy. The key element for system-level PDN analysis is a chip die model, which requires specialized EDA tools to create. These EDA solutions typically create chip models using either vector-based or vector-less dynamic current profiles. Vector-based chip model solutions are challenging to create and typically do not cover the complete ASIC die use case. In addition, the benefits of models created for the die, substrate, and PCB have multiple possible configurations such as lumped, distributed, looped and partial. This paper provides a novel workflow on the benefits of using lumped-looped models to improve efficiency, while achieving accuracy, and reducing the overall risk to a given system PDN. Lastly, this paper provides an improved methodology on how to know if the voltage ripple at the die bumps on a substrate is violating the defined specification of the ASIC and shows the methods on how to evaluate the PDN target impedance across a system.
DesignCon 2022 - DDR4-3200 FPGA-Based System With Interposer Power-Aware SI Simulation to Measurement Correlation
April 2022
Link to Paper
Abstract:
DDR4-3200 SSO channel modeling is further challenged to ensure DQ compliance specification for eye-opening at an ultra-low 1E-16 BER. As DDR4-3200 edge rates approach
DesignCon 2020 - Signal Integrity Characterization of Via Stubs on High Speed DDR4 Channels
January 2020
Link to Paper
Abstract:
As DDR data transmission rates continue to increase, the signal integrity of the DDR channel has become one of the most critical concerns. This article takes an extensive look at the impact of via stubs on the impedance of the signal lines on DDR4 memory, including test cases and ways to optimize design.
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