Technical Articles and Publications
APEC 2023 Professional Seminar - How Power Integrity Is Changing the World of Power Electronics
Link to Slides - COMING SOON
VRM MODELING AND STABILITY ANALYSIS FOR THE POWER INTEGRITY ENGINEER
Abstract: In the world of power electronics, the focus is on the power supply, and the load is modeled as a simple resistor. In the world of power integrity, the focus is on the decoupling capacitors required for the digital load, and the power supply is modeled as a simple resistor in series with an inductor. In the real world, neither assumption solves the problem of simulating the power delivery ecosystem with switching power supply control loops, gigabit switching digital loads, and a PCB network of filtering and decoupling components. The challenge is how to simulate the Power Integrity ecosystem and include the feedback loop and switching noise of a switch mode power supply (SMPS) without waiting days for the simulation results.
The solution presented here uses control loop theory state space equations to create a behavioral model of an SMPS that allows for fast simulation. This Sandler State Space Average Model previously published  has the fidelity to include the dynamic control loop behavior for stability assessment, large signal and small signal noise ripple, and power supply rejection ratio. The model also works with the Non-Invasive Stability Measurement method to assess the control loop phase margin from simple output impedance data.
Link to Paper HERE
Link to Slides HERE
DesignCon 2023 ChipHead - Hands-On PDN Impedance & Calibration Basics
Abstract: You have probably heard of calibration, de-embedding, and fixture removal for network analyzer measurements, but do you know how to do it for a 2-port shunt low-impedance measurement? Impedance measurements are a must-have skill for Power Integrity engineers. The measurements provide models for Capacitors, Resistors, and Inductors that work in both time and frequency domain simulations. Impedance measurements are also critical for verifying the performance stability of a power delivery network (PDN).
In this session, you’ll learn the difference between these terms. You’ll learn, with demonstrations, how to remove the impact of fixturing using calibration and de-embedding steps. The process works for both connectorized devices or with PCB browser probes to provide accurate measurements that are compatible with your PCB EM simulator.
Link to Slides HERE
Abstract: The voltage regulator module (VRM) is the foundation of power integrity. Due to their wide bandwidth and low cost, most newer VRM controllers employ transconductance feedback amplifiers, with the VRM manufacturers recommending a shunt compensation for the error amplifier design. However, most VRM designers and power integrity engineers may not be aware that they have another choice to improve the sensitivity and performance of their VRM design. The better performance of a current mode VRM with series compensation for the error amplifier is clearly demonstrated with simulations using the Sandler state-space average VRM model.
Additional analysis and discussion will be provided to show how the VRM’s performance has improved stability, reduced gain sensitivity, and overall improved performance with a series compensation network. A VRM case study will be presented in this technical session to show these performance improvements using the Sandler State Space Average model in Keysight PathWave ADS.
Link to Slides HERE
Abstract: The ASIC-based systems of today and tomorrow can no longer be designed by rules of thumb when it comes to power integrity. The current methods of evaluating power integrity for an ASIC die on a substrate are generally lacking sufficient accuracy. The key element for system-level PDN analysis is a chip die model, which requires specialized EDA tools to create. These EDA solutions typically create chip models using either vector-based or vector-less dynamic current profiles. Vector-based chip model solutions are challenging to create and typically do not cover the complete ASIC die use case. In addition, the benefits of models created for the die, substrate, and PCB have multiple possible configurations such as lumped, distributed, looped and partial. This paper provides a novel workflow on the benefits of using lumped-looped models to improve efficiency, while achieving accuracy, and reducing the overall risk to a given system PDN. Lastly, this paper provides an improved methodology on how to know if the voltage ripple at the die bumps on a substrate is violating the defined specification of the ASIC and shows the methods on how to evaluate the PDN target impedance across a system.
Link to paper HERE
Link to slides HERE
DDR4-3200 FPGA-based System with Interposer Power-Aware SI Simulation to Measurement Correlation
Abstract: DDR4-3200 SSO channel modeling is further challenged to ensure DQ compliance specification for eye-opening at an ultra-low 1E-16 BER. As DDR4-3200 edge rates approach < 100 ps, power-aware SI simulation is necessary to achieve higher fidelity modeling. The intent of this paper is to present methods for creating accurate power-aware signal integrity simulation which will demonstrate measurement correlation on the first DDR4-3200 FPGA memory controller, the Xilinx Versal, interfaced to a UDIMM with an interposer present during measurement.
This effort will combine simulation and measurement with the goal to show how to improve design margins during DDR4-3200 development cycles. Additionally, considerations and recommendations will be provided for higher-speed DDR5 designs with more complex power distribution, channel topologies, and receiver architectures.
Link to paper HERE
Link to slides HERE
Ultra-Ultra-Low Impedance (4 micro-ohm) Measurements
In this Extreme Measurements article, I discuss the lowered impedance targets that are a result of the increasing amount of current necessary for modern processor solutions. Read on to learn how to achieve impedance targets below 10 uOhms.
Measuring the Bulk Dielectric Constant (Dk) on a Microstrip with a TDR
Most modern circuit designs depend on accurate logic signals at the logic receiver. This assurance is based on the careful design of the signal path impedance, including printed circuit board (PCB) transmission lines, interconnects, vias, and cables.
If you have designed a controlled impedance transmission line based on a PCB stack-up, how do you know if the PCB fabrication house or another vendor built your stack-up to meet your controlled impedance specification? In fact, we have found, even after discussion with various laminate manufacturers, that the majority of dielectric constants specified in the vendor datasheet have uncertainty, with a lot of variability. This creates a call to action to measure these materials to get it right.
Common Cents Impedance Measurements
A technical article exploring different calibration techniques, with a 2-port probe, to archive to sub-100μΩ impedance measurements with U.S. pennies.
Partial Inductance - The secret to correlating simulation and measurement
There's confusion about the measurement of capacitors, and particularly the series inductance or ESL. Different manufacturers calibrate or de-embed their measurement differently, making it difficult to compare one vendor to another. The differences between these measurements represent different locations of the measurement reference plane.
When correlating EM simulation and measurement results, where should the reference plane be for the capacitor measurement? Why does the target impedance measurement show much higher inductance than the simulator? Why do some experts recommend measuring impedance from both sides of the PCB and not just one side? In this session, Steve Sandler, Heidi Barnes, and I will provide analysis that answers all of these questions and more!
TDR Measurement using the J2154A PerfectPulse® Differential TDR and the MSO68B Oscilloscope
Demonstrates how to use the the Picotest J2154A TDR with a MSO6 oscilloscope.
Calibrating the 2-Port Probe for Low Impedance PDN Measurements
Benjamin Dannan and Steve Sandler teamed up to explore the tradeoffs for various calibration methods and offer some recommendations and considerations to make accurate sub-milliohm impedance measurements.
Project X DDR4-2400 Signal Integrity Analysis
Northrop Grumman Case Study: Rigorous Design Analysis of a DDR4 DIMM-Based System
Analysis shows multi-board simulation model with custom ASIC, MCM package, PCBA, UDIMM, and RDIMM models
Best Paper Award Finalist and Winner of Best Paper Award at DesignCon 2020 for "Signal Integrity Characterization of Via Stubs on High Speed DDR4 Channels"
Link to paper: here
As DDR data transmission rates continue to increase, the signal integrity of the DDR channel has become one of the most critical concerns. This article takes an extensive look at the impact of via stubs on the impedance of the signal lines on DDR4 memory, including test cases and ways to optimize design.
This Best Paper Award was also republished on the Signal Integrity Journal in June 2020
Link to Article: Signal Integrity Characterization of Via Stubs on High Speed DDR4 Channels
2-Port Impedance Measurement using the P2102A Probe and E5061B VNA
Provides technical engineering procedure to setup and calibrate the P2102A 2-port probe using the E5061A VNA.
2-Port Impedance Measurement using the P2102A Probe and ZNL6 VNA
Provides technical engineering procedure to setup and calibrate the P2102A 2-port probe using the ZNL6 VNA.
2-Port Impedance Measurement using the P2102A Probe and Bode 100 VNA
Provides technical engineering procedure to setup and calibrate the P2102A 2-port probe using the Bode 100 VNA.
NISM using the P2102A Probe and E5061B VNA
Provides technical engineering procedure to setup and calibrate the P2102A 2-port probe using the E5061A VNA to complete Non-invasive stability margin (NISM) assessments of your voltage regulator modules (VRMs) for power integrity related applications..
DDR4-3200 Channel Modeling and Signal Integrity Analysis Using an FPGA
A presentation with the Xilinx VCK190 using the Versal on how to develop a DDR4-3200 simulation model. This looks at signal integrity in the channel, such as insertion loss, crosstalk, and tuning the DDR4 eye using ODT.
How Ground Bounce Can Ruin Your Day
Low-speed printed circuit board (PCB) designs now have to deal with high-speed switching problems. This article examines the ground bounce generated from an LCD assembly while evaluating the impact of the ground bounce on the system level EMI. Three solution strategies to mitigate the ground bounce are analyzed, the pros and cons of each strategy are provided along with the test results.
Addressing EMC Challenges with In-house EMC Pre-compliance Testing
An article on how to build an in-house EMC pre-compliance testing setup to improve the success rate in EMC compliance testing.
2-Port Impedance Measurement using the P2102A Probe and Copper Mountain Technologies 2-Port VNA
Provides technical engineering procedure to setup and calibrate the P2102A 2-port probe using the CMT VNA.