IR38164M

The IR38164 OptiMOS™ IPOL is an easy to use, fully integrated and highly efficient dc-dc regulator with Intel SVID and I2C/PMBus™ interfaces. The on-chip PWM controller and co-packaged low duty cycle optimized MOSFETs make the device a space-efficient solution, providing accurate power delivery for low output voltage and high current applications that require an Intel SVID interface. The IR38164 offers programmability of switching frequency, output voltage, and fault/warning thresholds and fault responses while operating over a wide input range. Providing flexibility as well as system level security in the event of fault conditions. The switching frequency is programmable from 500 kHz to 1.5 MHz for an optimum solution. The on-chip sensors and ADC along with the SVID, I2C and PMBus™ make it easy to monitor and report input voltage, output voltage, output current and temperature.

Applications: 

• Designed for Intel® single phase power rails requiring SVID communication such as VCCIO and VCMP on platforms such as VR13HC, VR13 and VR12.5. 

• Servers and High End Desktop CPU VRs for non-core applications 

• Telecom & Datacom Applications 

• Distributed Point of Load Power Architectures

Key Features:

The Sandler State-Space Average VRM model (SSAM) can be used for both frequency and time domain analyses:

• This model is designed to support true end-to-end power integrity simulation and modeling using Keysight ADS.

• VRM models provide small signal load ripple and large signal VRM switching ripple.

• Large signal analysis, including assessing large signal effects

• Small signal analysis

• Harmonic balance simulation

• Transient analysis

• AC analysis

• Phase noise analysis

• EMI Analysis

• Monte Carlo or worst-case circuit analysis

• Voltage ripple noise analysis

• VRM and power supply efficiency modeling

• Crosstalk analysis between power domains and sensitive signals

• PDN and impedance analysis

• Stability analysis (NISM, Bode - phase, gain, and stability margins)

• Input impedance, output impedance, startup, and transient step load response

• VRM control loop design, stability, and modeling

• Cascaded VRM and power supply analysis

• Cascaded VRM modeling

• DC drop analysis

• Voltage droop analysis

• Power Supply Rejection Ratio (PSRR) analysis

• Rogue wave analysis

• Target impedance analysis

• Supports multiphase designs – including current sharing between phases

• This model supports both DCM and CCM modes in addition to the voltage mode and current mode.

What's Included:

• Archived ADS library will be made available at checkout.

• The ADS library includes LTM4624 single-phase SSAM.

Pulling this model into an existing ADS workspace only requires a few mouse clicks.

Click here for our 4-step guide to help you add the SES Models to your ADS workspace.

Why Use a Sandler State-Space Model:

Behavioral models like SIMPLIS are available but are not designed to run fast with electromagnetic (EM) extracted S-parameter models representing the power distribution network (PDN) and cannot support end-to-end simulation.

The use of state-space average models for switched mode power supplies was started in the 1970s [1] and is an effective technique for averaging the switching behavior to get the small signal AC behavior of the switching power supply control loop in the frequency domain. Solving for the small signal behavior enables one to use that load-dependent operational point to drive the large signal switching behavior. This is what the Sandler-developed SSAM model does and makes it possible to simulate PSRR, power rail ripple, input/output impedances, switch node pulse width modulation (PWM), and regulator stability.

The SSAM is a behavioral model that simulates all noise sources going into and out of the switched mode power supply or voltage regulator module (VRM), as it is often called in the high-speed digital world.

This SSAM accurately predicts the complete VRM performance, while simple lumped models have limited use.

The SSAM, like any model, has its limits. It assumes that one is operating the regulator at a switching frequency at least six times higher than the control loop bandwidth. Keeping the VRM loop bandwidth less than 1/6th the switching frequency ensures a predictable behavior and avoids instabilities as one approaches the pulse width modulation switching frequency. At frequencies above 1/6th the switching frequency, it is the job of the PDN decoupling capacitors to deliver power.

For the highest-fidelity simulation and results, these models should be used with PCB and package effects to assess the true circuit performance.

References:

[1] S. Cuk and R. Middlebrook, “A general unified approach to modeling switching DC-to-DC converters in discontinuous conduction mode,” Power Electronics Specialists Conference, IEEE, 1977.