Background Today, voltage regulator modules (VRM) (and power supplies) need to supply power to multiple VDD cores to support FPGAs and/or custom ASICs using multi-gigabit ethernet, PCIe, and DDR memory interfaces. With that being said, vendor information for a VRM’s output impedance is not available and is not always accurate when it is supplied. Further, measuring ultra-low impedance on multiple VRMs or multi-topology DC-DC regulators is a challenge for any design engineer.
