Signal Integrity, Power Integrity, & EMC Blog 

Figure 1: DDR5 Interposer by EyeKnowHow Why Use DRAM Interposers for Signal Measurement? JEDEC standards define the DRAM input parameters at the ball of the DRAM, since it is the last point a probe can access for signal measurement. In practice, with designs becoming increasingly complex and compact, accessing the ball of the DRAM can be a challenge. Or sometimes, the closest measuring point is centimeters away, which will result in an inaccurate reading of the signal at the

What is Channel Operating Margin (COM)? You might be more familiar with Channel Operating Margin (COM) as it relates to IEEE 802.3 and OIF-CEI standards that use Phase-Amplitude-Modulation. For example, PAM-4 encodes four symbols per unit interval (UI), whereas NRZ modulation encodes one symbol per UI. A key advantage of PAM is that deployed hardware and existing PCB technology bins can achieve higher data-throughput rates by enhancing the modulation capability of PHY designs

In power integrity analysis, we primarily concern ourselves with the impedance response when evaluating the frequency domain. Specifically, we focus on the magnitude of the impedance response and tend to neglect the phase of the impedance response. After all, the phase can be extracted from the magnitude: Flat impedance magnitude across frequency is purely resistive with 0° phase -20 dB/decade slope is purely capacitive with a -90° phase +20 dB/decade slope is purely indu

Achieve First-Pass Success in AI and Chiplet Designs with Measurement-Validated SIPI Modeling The future of high-performance computing—AI accelerators, custom ASIC design, and complex Multi-Chip Modules (MCMs)—is defined by advanced packaging. However, as process nodes shrink and data rates soar past 112 Gbps , and even 224 Gbps , the package substrate has become the single greatest risk to performance and time-to-market. At Signal Edge Solutions, we don't just simulate; we