Signal Integrity, Power Integrity, & EMC Blog 

INTRODUCTION - WHY DO WE CARE ABOUT EMC? Let’s consider a scenario, as depicted by Figure 1, where an autonomous cleaning robot is cleaning in a hospital hallway moving past a room full of MRI machines that are in operation. In this scenario, let’s consider what would happen if this product was not designed to be robust enough to mitigate possible electromagnetic energy interference being radiated from the MRI machines. What are the risks? What is the product reputation impac

Benjamin Dannan and Steve Sandler Part 1 of 3 This article is the first part of a 3-part series focusing on the challenges of impedance measurement and PDN validation, including 2000 amp PDN and 2-port probe measurement techniques: Part 2 - The Measurement Result! Part 3 - The Measurement Result with another VNA Introduction Most of us are aware of the ground loop error in the 2-port measurement. Most of us are also aware that we need to introduce a ground loop isolator to co

Struggling to measure the open-loop gain of your power supply? Introduction and Application In the world of power electronics, the focus is on the power supply, where the challenge is developing an accurate model to use for simulation or measuring the gain to determine the power supply stability and performance. To create an accurate model for the power supply, the open-loop gain (AOL) and closed-loop plant gain of the power supply need to be understood. However, most power s

Background A TDR measurement (Time Domain Reflectometry) measures the reflections that result from a signal traveling through a transmission environment of some kind - a circuit board trace, a cable, a connector, and so on. In the past, a TDR was often a large, expensive instrument that included a high-speed edge pulse and a sampling oscilloscope. Today, TDR remains a great tool for maintaining signal integrity, used extensively to qualify vendor stack-ups, such as identifyin

Background Today, voltage regulator modules (VRM) (and power supplies) need to supply power to multiple VDD cores to support FPGAs and/or custom ASICs using multi-gigabit ethernet, PCIe, and DDR memory interfaces. With that being said, vendor information for a VRM’s output impedance is not available and is not always accurate when it is supplied. Further, measuring ultra-low impedance on multiple VRMs or multi-topology DC-DC regulators is a challenge for any design engineer.